混合訊號積體電路設計

臺北科技大學 115-1 學期課程，課號 366377。

課程大綱

This course offers an in-depth exploration into the analysis and design of mixed-signal integrated circuits (ICs), with a particular emphasis on signal conversion and system modeling. The curriculum is structured around four main pillars (MLDS) : (1) Modeling - the development of mixed-signal circuits, (2) Language - proficiency in programming languages such as Verilog-A, Verilog-D, Python, C, and Matlab, (3) Data/Signal - thorough analysis of circuit performance and signal quality, and (4) System - mastery in adaptive optimization algorithms. Practical examples, including voltage regulators, Phase-Locked Loops (PLLs), and Successive Approximation Register (SAR) Analog-to-Digital Converters (ADCs), will be used to reinforce learning.

課程進度

Week 1-3: Fundamentals of Closed-Loop Systems Week 4-5: MATLAB Modeling of PLL Week 6-7: Verilog-A Modeling of PLL Week 8: Mid-Term Project Assignment Week 9: Verilog-D Simulation of PLL Week 10: Circuit Synthesis Week 11-12: Mixed-Signal Simulation Techniques Week 14-15: Theoretical Concepts of SAR ADC Week 16-18: Final Project

評量方式

Prerequisites: 1. Fundamental Microelectronics 2. Basic VLSI Design 3. Familiarity with Computing Languages (MATLAB, Verilog, Python) Grading Distribution: • Homework Assignments: 30% • Attendance and In-Class Exercises: 10% • Mid-Term Project: 30% • Final Project: 30%

教材

【遵守智慧財產權觀念，請使用正版教科書，不得使用非法影印教科書】 使用外文原文書：否 References: 1. "CMOS Analog Circuit Design" by Allen 2024 Spring Assignment and Project Examples: ________________________________________________________________________________ 2024/3/4 MSD-HW1 PLL Linear Model Design Topic : PLL Linear Model Design Objective: Design an integer Phase-Locked Loop (PLL) with an output frequency determined by the formula: 2 GHz + 0.01 GHz multiplied by the last two digits of your student ID number. For instance, if your student ID is 110368130, your target output frequency should be set to 2.3 GHz. ________________________________________________________________________________ 2024/3/18 MSD-HW2 Stability analysis of the PLL circuit Topic : Stability analysis of the PLL circuit Objective: Design an integer Phase-Locked Loop (PLL) with an output frequency that is 2 GHz plus 0.01 GHz multiplied by the last two digits of your student ID. For example, if your student ID is 110368130, the target output frequency would be 2.3 GHz. _______________________________________________________________________________ 2024/4/1 MSD-HW3 Frequency hopping generation for Bluetooth Objective : Design a Frequency hopping PLL for the Bluetooth protocal. ________________________________________________________________________________ 2024/4/21 MSD-HW4 Resistance Computation of a ResistorMesh Network Topic: Resistance Computation of a ResistorMesh Network Objective: Determine the resistance between nodes A and B in a specified mesh network, where each resistor has a resistance of 10 Ω. Employ linear algebra techniques to calculate the resistance and validate the result using circuit simulation with Spectre. ________________________________________________________________________________ 2024/4/21 MSD-HW5A / MSD-HW5B Mixed Signal Generation MSD-HW5A : Topic : Generation of Continuous Frequency-Shift Keying (FSK) Waveform Objective: Generate a continuous Frequency-Shift Keying (FSK) waveform. This modulation technique uses varying frequencies to represent different data values, essential for understanding digital signal processing and telecommunications. ________________________________________________________________________________ MSD-HW5B : Topic: Sampled and Held (S/H) of the Triangular Spectrum Objective: - Generate an infinite-time domain single-cycle triangular waveform with a duration of 0.1 seconds, sample and hold the waveform at a rate of 0.01 seconds, and transform this signal into its spectrum using Fourier transform. ________________________________________________________________________________ General Submission Instructions: • Choose either MSD-HW5A or MSD-HW5B to implement. Completing both assignments is optional and will be highly regarded. • Submit your Python Jupyter notebook (.ipynb), containing the requested code and the plotted images, through Microsoft Teams before the deadline. ________________________________________________________________________________ MSD-Final : Topic: PLL Design Objective: This project provides an opportunity to apply learning to practical design challenges within the realm of mixed-signal integrated circuits. Students may choose to work individually or in pairs, exploring complex circuit design and integration, with an emphasis on both individual research and collaborative engineering solutions. Project Options: • Option (A): Individual Project - Integer Phase-Locked Loop (PLL) Design: Design an integer PLL independently, focusing on core principles and implementation techniques of PLL circuits. • Option (B): Collaborative Projects - (B.1) Fractional-N PLL with Sigma-Delta Modulator (SDM): Work in pairs to design a fractional-N PLL incorporating an SDM, suitable for applications requiring fine frequency resolution and stability. - (B.2) Integer PLL and SAR ADC Integration: Teams will design an integer